Software optimization for power consumption in DSP embedded systems

dc.contributor.advisorJulien, Christine, D. Sc.
dc.creatorTemple, Andrew Richarden
dc.date.accessioned2013-12-09T22:20:59Zen
dc.date.issued2012-05en
dc.date.submittedMay 2012en
dc.date.updated2013-12-09T22:20:59Zen
dc.descriptiontexten
dc.description.abstractThis paper is intended to be a resource for programmers needing to optimize a DSP’s power consumption strictly through software. The paper will provide a basic introduction into power consumption background, measurement techniques, and then go into the details of power optimization, focusing on three main areas: algorithmic optimization, taking advantage of hardware features (low power modes, clock control, and voltage control), and data flow optimization with a discussion into the functionality and power considerations when using fast SRAM type memories (common for cache) and DDR SDRAM. This work includes examples and results as tested on Freescale’s current state of the art Digital Signal Processors.en
dc.description.departmentElectrical and Computer Engineeringen
dc.format.mimetypeapplication/pdfen
dc.identifier.urihttp://hdl.handle.net/2152/22607en
dc.language.isoen_USen
dc.subjectLow poweren
dc.subjectClock gatingen
dc.subjectEmbedded programmingen
dc.subjectPower modesen
dc.titleSoftware optimization for power consumption in DSP embedded systemsen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorThe University of Texas at Austinen
thesis.degree.levelMastersen
thesis.degree.nameMaster of Science in Engineeringen

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