Hardware prefetchers' impact on memory access sampling: a case study on HeMem

Access sampling has emerged as an appealing technique for managing large-capacity memory systems, offering reduced overhead compared to traditional page table approaches characterized by lengthy page table walks and scans. However, this method faces challenges when hardware prefetchers inadvertently limit the information available for sampling, particularly regarding Last Level Cache (LLC) misses. These limitations can adversely affect the performance of certain workloads. HeMem, a user-level tiered memory management library, relies on Processor Event-Based Sampling (PEBS) to guide its management decisions. In this report, we assess various microbenchmarks exhibiting memory access patterns typically recognized by hardware prefetchers to investigate potential adverse effects. Our experiments reveal that when hardware prefetchers effectively recognize access patterns and prefetch data to caches, thus minimizing compulsory misses, HeMem's visibility into the access pattern is diminished, resulting in performance degradation. Additionally, we demonstrate that adjusting the sampling period of PEBS technology may offer a solution to mitigate these issues.