SiGe, SiGeC, and SiC MOSFET simulation, optimization, and fabrication

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Date

2002-12

Authors

Shi, Zhonghai

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Abstract

For more than 30 years, MOSFET device technology has been improving at a drastic rate mainly due to successful device scaling, and the resulting increasingly smaller device dimensions and higher device performance in terms of higher packing density, higher device speed, etc. However, challenges in scaling of CMOS technology into the nanometer regime are approaching physical limits, which are very difficult to overcome, if not impossible. Since MOSFET drive current depends on carrier mobility, one way to address the challenges of improving MOS transistor performance is to enhance carrier mobility in the MOSFET channel. Compressively-strained Si1-xGex alloys are very promising in terms of increasing hole mobility. In this work, sub-micron gate length buried Si1-xGex channel PMOSFET modeling, simulation, and optimization were studied using the MEDICI simulator, and an optimized device structure is obtained. 100 nm gate length Si1- xGex channel PMOSFETs have been simulated, and optimized by the combination of process simulation (TSUPREM4) and device simulation (MEDICI). The simulation results show that the benefits of high hole mobility in a Si1-xGex channel still hold below 100nm channel length. A 100nm channel length Si1-xGex, Si1-x-yGexCy and Si1-yCy PMOSFET process was established. Not only is device performance enhancement observed but also a desirable threshold voltage (VT) and small short channel effects (SCE) are achieved by device and process optimization. Drive current enhancements are demonstrated for 100nm channel length Si1-x-yGexCy and Si1-yCy PMOSFETs compared to Si control PMOSFETs, and C provides high temperature strain-stabilization for strained Si1-xGex channels. Device performance enhancement and ease of integration can be achieved simultaneously by using a smaller Ge mole fraction and Si cap layer optimization. It is also demonstrated that surface channel operation in the Si1-xGex PMOSFET with deposited HfO2 gate dielectrics can be used to recover mobility degradation due to the use of HfO2, and device performance enhancement and leakage current reduction is achievable with this concept. In order to fully exploit the high mobility benefits of Si1-xGex, Si1-x-yGexCy, or Si1-yCy alloys, a Ni silicide technique with low resistivity for these alloys has been developed for device applications.

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