Structured analog design in deep sub-micron technologies using CMOS inverters and current mirrors

dc.contributor.advisorViswanathan, T. R., doctor of electrical engineering
dc.contributor.advisorSun, Nan
dc.contributor.committeeMemberDodabalapur, Ananth
dc.contributor.committeeMemberAkinwande, Deji
dc.contributor.committeeMemberYan, Shouli
dc.creatorRaghunandan, Kolar Ranganathan
dc.creator.orcid0000-0002-2428-8542
dc.date.accessioned2018-02-05T21:46:45Z
dc.date.available2018-02-05T21:46:45Z
dc.date.created2017-12
dc.date.issued2017-12-05
dc.date.submittedDecember 2017
dc.date.updated2018-02-05T21:46:45Z
dc.description.abstractThe ubiquity of mobile computing devices and the ever increasing internet usage in recent years have led to a phenomenal growth in digital data traffic and burgeoned bandwidth demands on modern digital communication systems. These systems require mixed signal circuits operating at high sampling rates and complex digital signal processing (DSP) to achieve reliable performance. Circuit designs at these break-neck speeds require high speed devices provided by advanced CMOS technologies. Since, these processes can accommodate large number of devices per unit area; there is an urge to integrate more functionality on chip to reduce overall system cost. However, this presents several design challenges, such as minimizing process variations, reducing power dissipation and managing overall design/verification time. In addition, the traditional approach to design analog and mixed signal circuits, based on operational amplifiers (OP-AMP), is difficult in these technologies due to the low power supply voltage and reduced intrinsic gain of the transistors. Therefore, using stable large-gain and negative-feedback configurations to obtain precision has limited use in designing high speed analog circuits in these processes. This necessitates an alternative methodology for designing circuits for wide band applications. This research addresses the aforementioned problems by proposing a structured design methodology for analog and mixed signal integrated circuits for high speed applications. A set of analog modules based on the class-AB CMOS inverters and current mirrors are described to perform basic operations such as addition, subtraction, scaling and integration. The design approach uses replica-circuits extensively to control the large process, voltage and temperature (PVT) variations encountered in practice. The key idea is to independently control the logical threshold (V[underscore LT]) and the trans-conductance (g[underscore m]) of the CMOS inverter using control inputs from the replica and use it as a basic building block for designing higher level blocks and systems. Using this methodology, the designs of functional blocks namely, voltage references, filters, amplifiers, gyrators, comparators, multipliers, voltage-to-time converters and oscillators are presented. Finally, the measured results for prototypes fabricated in TSMC 180nm are presented that show the performance of these blocks in silicon.
dc.description.departmentElectrical and Computer Engineering
dc.format.mimetypeapplication/pdf
dc.identifierdoi:10.15781/T2PV6BQ16
dc.identifier.urihttp://hdl.handle.net/2152/63492
dc.language.isoen
dc.subjectAnalog circuits
dc.subjectAnalog building blocks
dc.subjectAmplifiers
dc.subjectFixed and variable gain elements
dc.subjectTransconductance elements
dc.subjectBandgap reference
dc.subjectCMOS squarer
dc.subjectCMOS 4-Q multiplier
dc.titleStructured analog design in deep sub-micron technologies using CMOS inverters and current mirrors
dc.typeThesis
dc.type.materialtext
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorThe University of Texas at Austin
thesis.degree.levelDoctoral
thesis.degree.nameDoctor of Philosophy

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