Layered syndrome based double error correcting codes for RRAM cells

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2023-05

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Abstract

Applications involving machine learning and neural networks have become increasingly essential in the AI revolution. Emerging trends in Resistive RAM memory technologies provide high-speed, low-cost, scalable solutions for such applications. These RRAM cells provide efficient and sophisticated memory hardware structures for machine-learning applications. However, it’s difficult to achieve reliable multilevel cell storage capacity in these memory technologies due to the occurrence of soft and hard errors. As these memories can store multi-bits per cell, it is important to explore limited magnitude symbols (multi-bit) error correction in RRAM. In this report, we propose a novel syndrome-based double error correcting code making efficient use of the inherent additive nature of RRAM cells for correcting errors in the symbol values. The proposed ECC divides the syndromes into groups and uses addition and XOR operations to correct double limited magnitude errors in the RRAM cells. It requires fewer checkbits, and since the memory itself can perform the addition through current summing, the decoder area and power are reduced.

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