System level tradeoffs between ASIC and FPGA accelerators
The demand for computing performance is ever increasing. However, more computing performance often requires more power, which incurs increased monetary cost and environmental impact. Thus, power efficiency, i.e., performance-per-watt, is becoming more and more important.
Specialized hardware accelerators are the best known and most promising way to improve power efficiency. They improve power efficiency by reducing or eliminating wasted work. Some common ways to implement accelerators are configurable circuits (FPGAs), application-specific circuits (ASICs), and application-specific processors (ASPs). Though there have been several works comparing some of these implementation methods, none have accounted for system aspects, including how well an accelerator adapts to changes and overheads incurred to use the accelerator such as the cost of data movement.
This thesis provides a more comprehensive comparison of accelerators. Firstly, this thesis presents a metric to quantify how well an accelerator adapts to changes and uses that metric to analyze different accelerator implementation methods (accelerator classes.) Secondly, this thesis identifies the overheads of moving data to/from accelerators and evaluates how different overheads impact different accelerator classes. Finally, this thesis presents a design space explorer that automatically performs the analysis and determines which accelerator class is preferable and when.
Our results show that each accelerator class is preferable in certain, non-trivial cases. The cases where FPGA-based accelerators are preferable is larger than previously thought.