Efficient optimization methods for analog/mixed-signal integrated circuits via machine learning



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During the analog design process, a significant amount of human effort is spent on optimizing circuit specifications by tuning the device parameters. Sizing device parameters is the task of obtaining satisfactory performance for certain constraint metrics and minimizing/maximizing other objective metrics. In general, an initial optimization is conducted based on schematic-level electrical simulations. However, the Analog/Mixed-Signal (AMS) Integrated Circuits (IC) design is also sensitive to the parasitics introduced during the layout. Therefore, a more comprehensive approach is to size device parameters under the consideration of layout parasitics. To automate this process, many automation methods are proposed where simulation feedback is integrated into the automation loop for an accurate evaluation of design choices. AMS simulations are typically costly to run; therefore, the automation method's cost is crucial. This dissertation proposes efficient automated solutions to solve the AMS sizing problem. First, this dissertation proposes a novel Machine Learning (ML) assisted evolutionary algorithm to tackle analog sizing problem. We address the data scarcity issue by introducing a data augmentation method that facilitates and improves the modeling of design metrics via Artificial Neural Networks (ANN). Further, we borrow techniques developed for evolutionary algorithms and introduce a parameter-free ranking methodology to differentiate design performance without human input. We assess the performance of our approach on several academic circuits and show that ML-based modeling significantly improves the simulation cost of the optimization algorithm. Second, in this dissertation, we study applying Reinforcement Learning~(RL) to solve analog sizing problem. We are influenced by the state-of-the-art policy gradient methods and tailor them to solve analog sizing task. Further, we include a recipe to extend this method for solving industrial-scale circuits with thousands of devices. We demonstrate the performance of our approach both on academic circuits and industrial circuits. We observe a significant performance improvement compared to several conventional baseline algorithms and compared to existing commercial tools. Then we visit the AMS tasks with varying simulations costs. Motivated by the fact that one typically needs to run multiple types of simulations, we leverage cheap-to-run simulations to make intermediate decisions on the potential quality of explored points. Then we refrain from expensive-to-run simulations if necessary. In addition, we introduce an asynchronously parallel framework and adapt our previous work for the case of designs with the differentiated cost of simulations. Our benchmarking shows that the proposed methods significantly reduce the total real-time optimization cost and the total CPU effort. Finally, this dissertation includes a solution on how to solve the sizing problem under layout effects effectively. We conduct a study to quantify the impacts of considering layout during transistor sizing. Then, we apply a Bayesian Neural Network~(BNN) based approach to solve the sizing problem. To include layout-induced parasitics, we extend our approach via Multi-Fidelity BNN, where the algorithm utilizes multiple information sources for efficient learning of post-layout performances. We also include a search-space exploration strategy using the trust-region approach, which is shown to be effective on problems with high number of input dimensions. Our tests suggest that the BNN-based sizing algorithm is very competitive compared to previous state-of-the-art algorithms. We further demonstrate that the co-learning strategy of Multi-Fidelity BNN further improves the efficiency, which is very crucial considering the costly post-layout simulations.


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