Mapping Addresses to L3/CHA Slices in Intel Processors

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dc.creatorMcCalpin, John D.
dc.date.accessioned2021-09-10T13:34:49Z
dc.date.available2021-09-10T13:34:49Z
dc.date.issued2021-09-10
dc.description.abstractThe distributed, shared L3 caches in Intel multicore processors are composed of “slices” (typically one “slice” per core), each assigned responsibility for a fraction of the address space. A high degree of interleaving of consecutive cache lines across the slices provides the appearance of a single cache resource shared by all cores. A family of undocumented hash functions is used to distribute addresses to slices, with different hash functions required for different numbers of slices. In all systems studied to date, the hash consists of a relatively short (16 to 16384 elements) “base sequence” of slice numbers, which is repeated with binary permutations for consecutive blocks of memory. The specific binary permutation used is selected by XOR-reductions of different subsets of the higher-order address bits. This report provides the base sequences and permutation select masks for Intel Xeon Scalable Processors (1st and 2nd generation) with 14, 16, 18, 20, 22, 24, 26, 28 slices, for 3rd Generation Intel Xeon Scalable Processors with 28 slices, and for Xeon Phi x200 processors with 38 slices.en_US
dc.description.departmentTexas Advanced Computing Center (TACC)en_US
dc.description.sponsorshipNational Science Foundation awards 1663578 and 1854828.en_US
dc.identifier.urihttps://hdl.handle.net/2152/87595
dc.identifier.urihttp://dx.doi.org/10.26153/tsw/14539
dc.language.isoengen_US
dc.relation.ispartofUT Faculty/Researcher Worksen_US
dc.relation.ispartofseriesACELab Technical Reports;TR-2021-03
dc.rightsAttribution-ShareAlike 3.0 United States*
dc.rights.restrictionOpenen_US
dc.rights.urihttp://creativecommons.org/licenses/by-sa/3.0/us/*
dc.subjectMicroprocessorsen_US
dc.subjectMulticore Processingen_US
dc.subjectCache Memoryen_US
dc.subjectSystem-on-Chipen_US
dc.subjectReverse Engineeringen_US
dc.titleMapping Addresses to L3/CHA Slices in Intel Processorsen_US
dc.typeTechnical reporten_US

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Technical Report: Mapping Addresses to L3/CHA Slices in Intel Processors
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BaseSequence_ICX_28-slice.txt
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Base Sequence for Ice Lake Xeon with 28 L3 slices
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Base Sequence for Xeon Phi x200 (Knights Landing) processor with 38 CHAs
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Base Sequence for Skylake Xeon processor with 14 L3 slices
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