Memristor logic design using driver circuitry

dc.contributor.assigneeBoard of Regents, The University of Texas System
dc.creatorEarl E. Swartzlander, Jr.
dc.creatorLauren Guckert
dc.date.accessioned2019-10-23T14:07:07Z
dc.date.available2019-10-23T14:07:07Z
dc.date.filed2016-12-05
dc.date.issued2019-01-01
dc.description.abstractA new lower-power gate design for memristor-based Boolean operations. Such a design offers a uniform cell that is configurable to perform all Boolean operations, including the XOR operation. For example, a circuit to perform the AND operation utilizes a first memristor and a second memristor connected in series. The circuit further includes a switch, where a node of the second memristor is connected to the switch. Furthermore, the circuit includes a third memristor connected to the switch in series, where the switch and the third memristor are connected in parallel to the first and second memristors. Additionally, the first voltage source is connected to the first memristor via a first resistor. In addition, a second voltage source is connected in series to the switch and the third memristor. In such a design, the delay is reduced to a single step and the area is reduced to at most 3 memristors.
dc.description.departmentBoard of Regents, University of Texas System
dc.identifier.applicationnumber15369364
dc.identifier.patentnumber10171083
dc.identifier.urihttps://hdl.handle.net/2152/76535
dc.identifier.urihttp://dx.doi.org/10.26153/tsw/3624
dc.publisherUnited States Patent and Trademark Office
dc.relation.ispartofUniversity of Texas Patents
dc.relation.ispartofUniversity of Texas Patents
dc.rights.restrictionOpen
dc.rights.restrictionOpen
dc.subject.cpcG11C13/003
dc.subject.cpcG11C13/0069
dc.subject.cpcH03K19/173
dc.titleMemristor logic design using driver circuitry
dc.typePatent

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