Electrical and material characteristics of hafnium-based multi-metal high-k gate dielectrics for future scaled CMOS technology: physics, reliability, and process development

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Date

2005

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Rhee, Se Jong

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Abstract

For the last four decades, the scaling down of physical thickness of SiO2 gate dielectrics has improved the speed of output drive current by shrinking of transistor area in front-end-process of integrated circuits. This technology trend has continuously produced new generation devices every 2 years in the field of both memory and non-memory devices. However, beyond the 100 nm technology node (gate length), the conventional SiO2 dielectric has reached its physical and electrical limitations, i.e., higher direct tunneling leakage current from its thin physical thickness would be one of the big issues to overcome. Especially, the application of thin SiO2 gate dielectric for low power operation in mobile devices such as PDA, cell phone, laptop computer or MP3 player would cause large standby power consumption, result in the degradation of its battery life. In viii addition, the reliability concern of the devices are more and more important because this thin SiO2 dielectric become more vulnerable to continuous stressing by the direct tunneling electrons. Therefore, the possible threshold voltage fluctuation of devices would be expected. Moreover, the SiO2 within this regime of thickness could be easily worn-out and eventually ended up with dielectric breakdown, causing a malfunction or failure of device. On the other hand, the dielectric permittivity of SiO2 (~ 3.9) could be a possible limitation for the future high speed device application such as MPU or ASIC of computers. In order to improve the speed of device, the dielectric material with higher permittivity (> 3.9) is inevitable. For these reasons, the highk gate dielectrics have been intensively investigated in order to possibly replace the conventional SiO2 in silicon technology. Since high-k dielectrics provide the same capacitance with a thicker film, the leakage current reduction, therefore, less the standby power consumption is one of the huge advantages. Also, it is easier to fabricate during the process because the control of film thickness is still not in the critical range compared to the same leakage current characteristic of SiO2 film. If high-k dielectrics are scaled down to similar thickness of conventional SiO2, the electrical characteristics such as drive current, transconductance, etc., would be improved due to the higher dielectric permittivity. ix The studies in this field have been focusing on adaptable high-k materials to Si substrate with conventional CMOS process, such as Hf, Zr, or La based binary metal oxide and their silicates. Among them, the hafnium oxide (HfO2) has received a great deal of attention, and seems to be the most promising high-k dielectric so far. The HfO2 has know to have a dielectric constant (22 ~ 25), a relatively large energy bandgap (~ 5.7 eV) with sufficient band offsets with silicon (∆Ec ~ 1.5 eV and ∆Ev ~ 3.1 eV), and a good thermally stability in contact with silicon and metal gates. Although a significant amount of experimental work to understand the basic characteristics of HfO2 has been conducted, there are still much remaining challenges: e.g. low immunity to oxygen and boron, crystallization at high temperature, and channel mobility degradation. In this research, the focus is primarily placed on the understanding of HfO2 high-k dielectric material in terms of device physics, reliability, and application for process development. The effect of charges in HfO2 to device characteristics and the role of its interfacial layer are studied. The charge trapping characteristics of HfO2 under external AC and DC stress, and the device lifetime with stress condition are examined. The Hf-based multi-metal gate dielectric is developed to overcome the drawbacks of HfO2. Improved material and electrical characteristics are reviewed.

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