Exploring shared data caches for network processors

Exponential link bandwidth increase over the past decade has sparked off interest in increasingly complex packet processing applications. To provide flexible and high-performance systems supporting these applications, a new breed of processors called Network Processors has emerged. These processors face an intensified Memory wall problem. They do not employ latency reducing techniques and instead rely on latency hiding techniques alone. Prior work has shown that this approach is inherently limited by the off-chip memory bandwidth. In this context, we analyze the effectiveness of a centralized data cache shared among all the processing cores of a Network Processor. We show that high hit-rates observed translate into significant improvement in processor utilization levels in memory bandwidth constrained environments. We also investigate a software based cache implementation with a goal to provide the benefit of data caching in current generation of Network Processors (that lack hardware data caches). We highlight various issues that constrain the design and implementation of a software cache on the IXP class of Network Processors