New test vector compression techniques based on linear expansion




Chakravadhanula, Krishna V.

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This dissertation considers the problem of reducing the storage as well as the bandwidth (data transfer rate between tester and chip) requirements of automatic test equipment (i.e., testers). Several new test vector compression schemes based on linear expansion are presented. The compressed test vectors are stored on the tester and transferred to the chip where a linear expansion network is used to decompress them. The lossless compression techniques described here significantly reduce the test data stored on the tester compared with conventional external testing, but do not require the hardware overhead and complexity of full stand-alone built-in self-test (BIST). One of the contributions of this dissertation is efficient compression techniques that do not require any constraints on the automatic test pattern generation (ATPG) process, thus simplifying the design flow. A new form of linear feedback shift register (LFSR) reseeding is described which allows partial dynamic reseeding and achieves greater encoding efficiencies than previous forms of LFSR reseeding. A new hybrid BIST scheme is proposed that uses an “incrementally guided LFSR” to provide very attractive tradeoffs between test length and tester storage requirements while using very simple vii on-chip hardware. A technique is described that combines LFSR reseeding and statistical coding in a powerful way by taking advantage of the large solution space of linear equations to find LFSR seeds that can be efficiently encoded using a statistical code. A new scheme for combinational linear expansion is proposed that uses adjustable width expansion to eliminate the need that every scan bit-slice be in the output space of the linear decompressor, while providing greater compression than fixed width expansion techniques. Finally, a compression scheme is described that combines three different stages of linear expansion to achieve extremely high encoding efficiencies while requiring low hardware overhead as it configures the decompressor out of the scan cells themselves. Both the adjustable width and 3-stage decompression schemes provide the nice feature that any scan vector can be efficiently compressed regardless of the number or distribution of specified bits, thus allowing the use of any ATPG procedure without any constraints.