Placement for structured ASICs

dc.contributor.advisorPan, David Z.en
dc.contributor.committeeMemberMcdermott, Marken
dc.creatorKumar, Anurag, 1983-en
dc.date.accessioned2010-08-25T15:49:04Zen
dc.date.available2010-08-25T15:49:04Zen
dc.date.available2010-08-25T15:49:09Zen
dc.date.issued2009-12en
dc.date.submittedDecember 2009en
dc.date.updated2010-08-25T15:49:09Zen
dc.descriptiontexten
dc.description.abstractStructured ASICs provide an exciting middle-ground between ASIC and FPGA design styles because they provide trade-off between the high per- formance of ASIC design and low costs of FPGA design. To fully utilize the benefits of structured ASIC, placement stage must be aware of the modularity of the structured ASIC architecture. This work describes a novel solution to placement of structured ASICs. Integer linear programming formulation is proposed for satisfying the constraints associated with structured ASIC clock architecture. Regularity of the platform is exploited during legalization and wirelength recovery stages to speed-up the detailed placement stage. Our methods show overall wirelength reduction up to 33% and up to 3X speedup compared to other placers.en
dc.description.departmentElectrical and Computer Engineering
dc.format.mimetypeapplication/pdfen
dc.identifier.urihttp://hdl.handle.net/2152/ETD-UT-2009-12-430en
dc.language.isoengen
dc.subjectPlacement, Vlsien
dc.titlePlacement for structured ASICsen
dc.type.genrethesisen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorThe University of Texas at Austinen
thesis.degree.levelMastersen
thesis.degree.nameMaster of Science in Engineeringen

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