Improving test compression and diagnosis for system-on-chip designs

dc.contributor.advisorTouba, Nur A.
dc.contributor.committeeMemberPan, Zhigang
dc.contributor.committeeMemberOrshansky, Michael
dc.contributor.committeeMemberGharpurey, Ranjit
dc.contributor.committeeMemberSuleman, Muhammad A
dc.creatorSaleem, Kamran, Ph. D.
dc.creator.orcid0000-0002-1491-8328
dc.date.accessioned2019-01-29T16:13:05Z
dc.date.available2019-01-29T16:13:05Z
dc.date.created2016-12
dc.date.issued2016-12
dc.date.submittedDecember 2016
dc.date.updated2019-01-29T16:13:06Z
dc.description.abstractThis dissertation presents new approaches to improve test compression and fault diagnosis for system-on-chip (SOC) designs. SOCs typically contain one or more embedded processors which can be used to aid in test and diagnosis. Novel techniques are presented for test vector compression and output response compaction running in software on an embedded processor, and for diagnosis from compactor signatures. The proposed test compression technique is based on a novel algorithm called Recursively Defined Invertible Sets (RDIS). It exploits the abundance of don’t cares in industrial test data and achieves large amounts of compression. The compressed data is stored on the tester and transferred on-chip to be decompressed by the software program. A test response compaction technique is proposed and implemented in software. Unlike previous techniques for software based test response compaction, the proposed approach is able to handle output responses with unknown (X) values. The methodology is based on canceling out X's in response signatures while using cost-effective X masking as a preprocessing step. The results indicate significant improvement in compression compared with previous approaches. A fundamentally new technique for precisely identifying error locations from output response signatures for propagation cones reaching fewer scan cells than the size of the MISR is described. The proposed approach does not require any additional hardware or extra data to be collected. It uses off-line software-based processing to extract information from signatures to deduce error locations even when there are a large number of errors. Experimental results demonstrate the reductions in suspect set size that can be obtained with the proposed techniques. The above diagnosis technique is further improved by a novel circuit partitioning technique that adds observation points to observe faults before they can spread out to too many primary outputs. An extra MISR is introduced to compact the data form these observation points. By careful selection of the location of the observation points, the maximal propagation cone for any fault to one of the MISRs is kept small enough to allow precise diagnosis of the error locations. All the aforementioned methods are described in detail along with experimental results.
dc.description.departmentElectrical and Computer Engineering
dc.format.mimetypeapplication/pdf
dc.identifierdoi:10.15781/T2WW77M16
dc.identifier.urihttp://hdl.handle.net/2152/72489
dc.language.isoen
dc.subjectTest compression
dc.subjectDiagnosis
dc.subjectCompaction
dc.subjectMISR
dc.subjectPropagation cones
dc.titleImproving test compression and diagnosis for system-on-chip designs
dc.typeThesis
dc.type.materialtext
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorThe University of Texas at Austin
thesis.degree.levelDoctoral
thesis.degree.nameDoctor of Philosophy

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