Characterization of voltage noise in big, small and single-ISA heterogeneous systems

dc.contributor.advisorJohn, Lizy Kurian
dc.contributor.committeeMemberReddi, Vijay Janapa
dc.creatorGarg, Ankita
dc.date.accessioned2016-09-23T14:48:21Z
dc.date.available2016-09-23T14:48:21Z
dc.date.issued2013-05
dc.date.submittedMay 2013
dc.date.updated2016-09-23T14:48:22Z
dc.description.abstractSensitivity of the microprocessor to voltage fluctuations is becoming a major concern with growing emphasis on designing power-efficient microprocessors. Voltage fluctuations that exceed a certain threshold cause "emergencies" that can lead to timing errors in the processor, thus risking reliability. To guarantee correctness under such conditions, large voltage guardbands are employed, at the cost of reduced performance and wastage of power. Trends in microprocessor technology indicate that worst-case operating voltage margins are not sustainable. Since voltage emergencies occur only infrequently, resilient architectures with aggressive guardbands are needed. However, to enable the exploration of the design space of resilient processors, it is important to have a deep understanding of the characteristics of voltage noise in different system configurations. Prior research in this area has mostly focused on systems with very few cores. Given the increasing relevance of large multi-core systems, this thesis presents a detailed characterization of voltage noise on chip multi-processors, consisting of large number of cores. The data indicates that while the worst case voltage droop increases with increase in the number of cores, the frequency of occurrence of the droops is not greatly impacted, emphasizing the feasibility of employing resilient microarchitectures with aggressive voltage margins. The thesis also presents a comparative study of voltage noise in CMPs consisting of either high-performant out-of-order cores and power-efficient in-order cores. The study highlights that the out-of-order cores experience much larger voltage variations when compared to the in-order cores, but offer a clear advantage in terms of performance. Experiments indicate that in-order configurations that offer equivalent performance to the out-of-order cores result in large energy-delay product, indicating the trade-offs involved in designing for performance, power and reliability. The thesis also presents a study of voltage noise in single-ISA heterogeneous configurations, to highlight the benefits of such systems towards lowering the worst-case voltage margins, which improve both performance and power. The experimental results indicate that the worst-case voltage droop in such heterogeneous systems lies in between the out-of-order and in-order cores and provide reasonable power-efficiency and performance. Further, the work highlights the importance of exploring the design-space of heterogeneous systems considering reliability as an important design criteria.
dc.description.departmentComputer Sciences
dc.format.mimetypeapplication/pdf
dc.identifierdoi:10.15781/T2GX44W11
dc.identifier.urihttp://hdl.handle.net/2152/40992
dc.subjectVoltage noise
dc.subjectMulti-cores
dc.subjectSingle-ISA heterogeneous
dc.subjectPower modeling
dc.subjectVoltage modeling
dc.subjectReliability
dc.titleCharacterization of voltage noise in big, small and single-ISA heterogeneous systems
dc.typeThesis
dc.type.materialtext
thesis.degree.departmentComputer Sciences
thesis.degree.disciplineComputer Science
thesis.degree.grantorThe University of Texas at Austin
thesis.degree.levelMasters
thesis.degree.nameMaster of Science in Engineering

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