Main-memory near-data acceleration with concurrent host access
dc.contributor.advisor | Erez, Mattan | |
dc.contributor.committeeMember | Orshansky, Michael | |
dc.contributor.committeeMember | Gerstlauer, Andreas | |
dc.contributor.committeeMember | Caramanis, Constantine | |
dc.contributor.committeeMember | Beard, Jonathan | |
dc.creator | Cho, Benjamin Youngjae | |
dc.date.accessioned | 2021-07-16T21:28:47Z | |
dc.date.available | 2021-07-16T21:28:47Z | |
dc.date.created | 2021-05 | |
dc.date.issued | 2021-04-13 | |
dc.date.submitted | May 2021 | |
dc.date.updated | 2021-07-16T21:28:47Z | |
dc.description.abstract | Processing-in-memory is attractive for applications that exhibit low temporal locality and low arithmetic intensity. By bringing computation close to data, PIMs utilize proximity to overcome the bandwidth bottleneck of a main memory bus. Unlike discrete accelerators, such as GPUs, PIMs can potentially accelerate within main memory so that the overhead for loading data from main memory to processor/accelerator memories can be saved. There are a set of challenges for realizing processing in the main memory of conventional CPUs, including: (1) mitigating contention/interference between the CPU and PIM as both access the same shared memory devices, and (2) sharing the same address space between the CPU and PIM for efficient in-place acceleration. In this dissertation, I present solutions to these challenges that achieve high PIM performance without significantly affecting CPU performance (up to 2.4\% degradation). Another major contribution is that I identify killer applications that cannot be effectively accelerated with discrete accelerators. I introduce two compelling use cases in the AI domain for the main-memory accelerators where the unique advantage of a PIM over other acceleration schemes can be leveraged. | |
dc.description.department | Electrical and Computer Engineering | eng |
dc.format.mimetype | application/pdf | |
dc.identifier.uri | https://hdl.handle.net/2152/86866 | |
dc.identifier.uri | http://dx.doi.org/10.26153/tsw/13817 | |
dc.language.iso | en | |
dc.subject | Processing in memory | |
dc.subject | Near-data processing | |
dc.subject | Machine learning | |
dc.subject | Deep learning | |
dc.subject | Main memory | |
dc.subject | Main-memory acceleration | |
dc.title | Main-memory near-data acceleration with concurrent host access | |
dc.type | Thesis | |
dc.type.material | text | |
thesis.degree.department | Electrical and Computer Engineering | |
thesis.degree.discipline | Electrical and Computer Engineering | |
thesis.degree.grantor | The University of Texas at Austin | |
thesis.degree.level | Doctoral | |
thesis.degree.name | Doctor of Philosophy |
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