Design of radix 4 divirs using high redundancy in 65 nanometer CMOS technology

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Date

2005

Authors

Pham, Tung Nang

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Abstract

As technology keeps changing, there is a need to explore different design tradeoffs and alternatives. In the old technologies where die area is very important and transistors are slow, it would make sense to avoid an adder for quotient conversion and speed up division by doing on-the-fly conversion – as found in radix 4 minimally redundant dividers. By the same token, in a new technology where many millions of transistors are available in a relatively small silicon area, it is beneficial to use an adder and high degree of redundancy to simplify quotient selection and conversion. A number of radix 4 maximally redundant and overredundant dividers are designed and implemented in 65 nm CMOS technology using an ASIC flow and triple VT devices. The results show that clock and data gating saves up to ~30% power with a minimal area and timing overhead. The results also show that the radix 4 maximally redundant dividers outperform the radix 4 overredundant dividers. One design of the radix 4 maximally redundant dividers operates at a cycle time of ~1.9 ns and consumes ~5 mW of power and ~19 µW of leakage power. For a double precision division, it has a latency of ~55 ns and spends ~290 pJ of energy.

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