Supporting compiler-driven FPGA virtualization
| dc.contributor.advisor | Rossbach, Christopher J. | |
| dc.creator | Yang, Tiffany Ya | |
| dc.date.accessioned | 2021-09-07T20:42:05Z | |
| dc.date.available | 2021-09-07T20:42:05Z | |
| dc.date.created | 2020-08 | |
| dc.date.issued | 2020-09-14 | |
| dc.date.submitted | August 2020 | |
| dc.date.updated | 2021-09-07T20:42:05Z | |
| dc.description.abstract | Many cloud providers now support on-demand FPGA acceleration in data centers. Though FPGAs can exceed general-purpose CPU performance by orders of magnitude, they introduce challenges that limit their popularity. Virtualization provides programmability and cost-effectiveness, two features that are critical to making FPGAs accessible as a mainstream acceleration technology. One recently proposed system to virtualize FPGAs is Synergy. Synergy provides suspend and resume, program migration, spatial and temporal multiplexing, and portability. These capabilities are enabled by extending features from the Cascade JIT compiler [52] and the AmorphOS runtime system [31]. Because Synergy provides compiler-based state capture, it does not require hardware support. This makes it deployable on devices available in data centers today. Using Synergy to virtualize an application comes with a performance cost of 3 − 4× that of an unvirtualized application and an increase in FPGA resource utilization. These overheads are primarily due to the mechanism Synergy uses to manage each stateful value in the application. Many applications periodically reach quiescent points during execution, when their state is limited to a subset of stateful variables, which can reduce these overheads. We implemented a quiescence interface in both AmorphOS and Synergy. A benchmark with substantial in-flight state was modified to use the quiescence interface, and it suffers one order of magnitude less performance degradation during state capture. This work also discusses the challenges of adapting a deep neural network accelerator on Synergy. | |
| dc.description.department | Computer Science | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | https://hdl.handle.net/2152/87501 | |
| dc.identifier.uri | http://dx.doi.org/10.26153/tsw/14445 | |
| dc.language.iso | en | |
| dc.subject | Reconfigurable logic and FPGAs | |
| dc.subject | Just-in-time compilers | |
| dc.subject | Virtualization | |
| dc.title | Supporting compiler-driven FPGA virtualization | |
| dc.type | Thesis | |
| dc.type.material | text | |
| thesis.degree.department | Computer Sciences | |
| thesis.degree.discipline | Computer Science | |
| thesis.degree.grantor | The University of Texas at Austin | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science in Computer Sciences |
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