Switch-based Fast Fourier Transform processor

dc.contributor.advisorSwartzlander, Earl E.en
dc.creatorMohd, Bassam Jamil, 1968-en
dc.date.accessioned2012-10-05T17:35:22Zen
dc.date.available2012-10-05T17:35:22Zen
dc.date.issued2008-12en
dc.descriptiontexten
dc.description.abstractThe demand for high-performance and power scalable DSP processors for telecommunication and portable devices has increased significantly in recent years. The Fast Fourier Transform (FFT) computation is essential to such designs. This work presents a switch-based architecture to design radix-2 FFT processors. The processor employs M processing elements, 2M memory arrays and M Read Only Memories (ROMs). One processing element performs one radix-2 butterfly operation. The memory arrays are designed as single-port memory, where each has a size of N/(2M); N is the number of FFT points. Compared with a single processing element, this approach provides a speedup of M. If not addressed, memory collisions degrade the processor performance. A novel algorithm to detect and resolve the collisions is presented. When a collision is detected, a memory management operation is executed. The performance of the switch architecture can be further enhanced by pipelining the design, where each pipeline stage employs a switch component. The result is a speedup of Mlog2N compared with a single processing element performance. The utilization of single-port memory reduces the design complexities and area. Furthermore, memory arrays significantly reduce power compared with the delay elements used in some FFT processors. The switch-based architecture facilitates deactivating processing elements for power scalability. It also facilitates implementing different FFT sizes. The VLSI implementation of a non-pipeline switch-based processor is presented. Matlab simulations are conducted to analyze the performance. The timing, power and area results from RTL, synthesis and layout simulations are discussed and compared with other processors.en
dc.description.departmentElectrical and Computer Engineeringen
dc.format.mediumelectronicen
dc.identifier.urihttp://hdl.handle.net/2152/18192en
dc.language.isoengen
dc.rightsCopyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.en
dc.subject.lcshSignal processing--Digital techniques--Equipment and supplies--Design and constructionen
dc.subject.lcshMicroprocessors--Design and constructionen
dc.subject.lcshComputer architectureen
dc.subject.lcshTelecommunication--Switching systems--Equipment and supplies--Design and constructionen
dc.subject.lcshComputers, Pipeline--Design and constructionen
dc.subject.lcshMemory management (Computer science)en
dc.subject.lcshComputer storage devicesen
dc.titleSwitch-based Fast Fourier Transform processoren
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorThe University of Texas at Austinen
thesis.degree.levelDoctoralen
thesis.degree.nameDoctor of Philosophyen

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