Parallel associative processor formed from modified dram

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dc.contributor.assigneeBoard of Regents, The University of Texas System
dc.creatorLipovski, G. Jack
dc.date.accessioned2019-10-23T21:40:45Z
dc.date.available2019-10-23T21:40:45Z
dc.date.filed1996-08-05
dc.date.issued1997-12-02
dc.description.abstractA parallel associative processor is formed from a DRAM circuit whose storage positions are organized into words, which are further subdivided into columns. Each column is associated with a sense amplifier, which is used to perform data refreshing. Comparators are coupled to the sense amplifiers to permit logical operations, including comparisions with external data placed on a bus, to be performed on data addressed and read from the storage positions, including during refresh operations. A latch or flip-flop with control inputs is associated with each word, to hold a match or mismatch signal identifying, in parallel for each word, the results of the logical operations.
dc.description.departmentBoard of Regents, University of Texas System
dc.identifier.applicationnumber8695125
dc.identifier.patentnumber5694406
dc.identifier.urihttps://hdl.handle.net/2152/77257
dc.identifier.urihttp://dx.doi.org/10.26153/tsw/4346
dc.publisherUnited States Patent and Trademark Office
dc.relation.ispartofUniversity of Texas Patents
dc.relation.ispartofUniversity of Texas Patents
dc.rights.restrictionOpen
dc.rights.restrictionOpen
dc.subject.cpcG06F12/0866
dc.subject.cpcG06F7/02
dc.subject.cpcG06F16/90339
dc.subject.cpcG06F2207/025
dc.subject.cpcG11C7/1006
dc.subject.cpcG11C11/406
dc.subject.cpcG11C15/04
dc.subject.cpcG11C15/043
dc.subject.uspc714/805
dc.titleParallel associative processor formed from modified dram
dc.typePatent

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