Parallel associative processor formed from modified dram
A parallel associative processor is formed from a DRAM circuit whose storage positions are organized into words, which are further subdivided into columns. Each column is associated with a sense amplifier, which is used to perform data refreshing. Comparators are coupled to the sense amplifiers to permit logical operations, including comparisions with external data placed on a bus, to be performed on data addressed and read from the storage positions, including during refresh operations. A latch or flip-flop with control inputs is associated with each word, to hold a match or mismatch signal identifying, in parallel for each word, the results of the logical operations.