Methods for nano-precise overlay in advanced in pick-and-place assembly




Ajay, Paras

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We have explored two nanofabrication techniques in this thesis – Jet-and-Flash Imprint Lithography (J-FIL), and Nano-precise Modular Assembly of Pre-fabricated blocks (N-MAP), with a focus on nano-precise overlay in these techniques. J-FIL currently uses template shape-and-size control, along with x-y-q substrate position control, to overlay template patterns to substrate patterns. This method is designed to mix-and-match with photolithography (PL) and corrects distortions over a limited field size of 26mm x 33mm. Template shape-and-size control, by itself, does not perform well for multi-field templates because of inter-field mechanical coupling, along with limits on the maximum lateral forces that can be applied on the template. We have explored new methods to achieve sub-5nm overlay in multi-field patterning, including thermal-actuation based substrate-distortion-control, and genetic algorithm-based template topology-optimization. Separately, we have realized that localized overlay errors can be introduced in J-FIL due to sub-micron sized particles, which are often present between the wafer and the wafer chuck. We have developed new compliant chuck designs to address this problem. While the above overlay control methods are developed for J-FIL, they are set up to ultimately be integrated into another technique – N-MAP. This technique has the potential to facilitate a variety of new nanofabrication applications, including 3D ICs and secure super-sized SoCs, by enabling nano-precise assembly of pre-fabricated device blocks (PFBs). N-MAP incorporates a vacuum-based superstrate (in place of the template in J-FIL), which is designed to pick up PFBs and to place them at precise locations on a product substrate. In this dissertation we present process flows for N-MAP, designs for the vacuum-based superstrate, as well as a simulation framework to analyze the pickup and placement mechanics of N-MAP. Additionally, we’ve explored various technology options for the source wafers in N-MAP, which need to contain a buried sacrificial layer to enable nano-precise pick-and-place assembly


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