Protein-mediated nanocrystal assembly for floating gate flash memory fabrication

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Date

2008-12

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Tang, Shan, 1975-

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Abstract

As semiconductor device scaling is reaching the 45 nm node, the need for novel device concept, architecture and new materials has never been so pressing as today. Flash memories, the driving force of semiconductor memory market in recent years, also face the same or maybe more severe challenges to meet the demands for high-density, low-cost, low-power, high-speed, better endurance and longer retention time. As traditional continuous floating gate flash struggles to balance the trade-off between high speed and retention requirement, nanocrystal (NC) floating gate flash has attracted more and more interest recently due to its advantages over traditional flash memories in many areas such as better device scaling, lower power consumption and improved charge retention. However, there are still two major challenges remaining for embedded NC synthesis: the deposition method and the size and distribution control. Nowadays using bio-nano techniques such as DNA, virus or protein for NC synthesis and assembly has become a hot topic and feasible for actual electronic device fabrication. In this dissertation a new method for NC deposition wherein a colloidal suspension of commercially-available NCs was organized using a self-assembled chaperonin array. The chaperonin array was applied as a scaffold to mediate NCs into an assembly with uniform spatial distribution on Si wafers. By using this method, we demonstrated that colloidal PbSe and Co NCs in suspension can self-assemble into ordered arrays with a high density of up to 10¹²cm⁻². MOSCAP and MOSFET memory devices were successfully fabricated with the chaperonin protein mediated NCs, showing promising memory functions such as a large charge storage capacity, long retention time and good endurance. The charge storage capacity with respect to material work function, NC size and density was explored. In addition to NC engineering, the tunnel barrier was engineered by replacing traditional SiO₂ by high-k material HfO₂, giving a higher write/erase speed with a reduced effective oxide thickness (EOT). Suggestions for future research in this direction are presented in the last part of this work.

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