Applying Universal Verification Methodology on a Universal Asynchronous Receiver/ Transmitter design
Universal asynchronous receiver/ transmitter (UART) is a computer hardware device that is used to transform user data to parallel and serial forms. The UART protocol is typically integrated in an Integrated Circuit (IC) which is used for serial communication over a computer or a peripheral device. The UART protocol accepts the input data as bytes and transmits the single bits in a sequential way. Usually, there will one or more UART peripherals which are integrated in microcontrollers and related devices which can support synchronous operation. The UART communication method may be done in three different ways: simplex (in one direction only), full duplex (both devices can receive and send data simultaneously) and half duplex (both devices can take turns to receive and transmit data). The structure of the data frame contains a single start bit, followed by next five to nine bits, depends on the code set employed. If there is a parity bit, then it will be placed after all the data bits. The next one or two bits are always logic high to indicate the stop bit(s). This technical report will demonstrate a verification methodology to verify WISHBONE UART IP Core using the Universal Verification Methodology (UVM) process.