Technology computer aided design and analysis of novel logic and memory devices
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Novel logic and memory device concepts are proposed and analyzed. For the latter purpose the commercial technology computer aided design (TCAD) simulators Taurus and Sentaurus Device by Synopsys are used. These simulators allow ready definition of complex device geometries. Moreover, while not all device physics models are state-of-the-art, the wide variety of device physics considered is advantageous here when not all of the critical device physics is known a priori. The initial device concept analyzed was a one transistor (1T), one capacitor (1C) – pseudo-static random access memory (SRAM). Simulations indicate that tri-gate pass-transistors will offer better gate control and reduced leakage, and tri-gate capacitors will offer increased capacitance, making the overall device performance comparable to SRAM. The second device analyzed was a quantum dot non-volatile memory. In principle, such memories become more reliable for a given tunnel oxide thickness by localizing any leaks to individual dots. However, simulations illustrate limits on dot packing density to retain this advantage due to inter-dot tunneling. The final device, proposed and extensively analyzed here, is a novel tunnel field-effect transistor (TFET), the “hetero-barrier TFET” (HetTFET). In complementary metal-oxide-semiconductor (CMOS) logic, while switching power decreases with voltages, standby power increases due to thermionic emission of charge carriers over the source-to-channel barrier in the constituent metal-oxide-semiconductor field-effect transistors (MOSFETs). As a result, CMOS voltage and, thus, power scaling is approaching an impasse. Because TFETs are not subject to thermionic emission, they are being considering as a replacement for MOSFETs. Various materials systems and device geometries have been considered. However, even in simulation, balancing switching and standby power at low voltages while still providing sufficient transconductance for rapid switching has not proven straightforward. HetTFETs are intended to achieve high on-to-off current ratios via a threshold defined by the onset of band overlap, and high ON-state transconductances via tunneling through thin barriers defined by crystal growth, rather than relying on gate-controlled barrier narrowing in whole or part for either purpose as with other designs. Simulations of n and p-channel HetTFETs suggest the possibility of current CMOS-like performance at much lower voltages.