Fault clearance in distributed power architectures with limited energy flow through power electronic interfaces
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The objective of this thesis is to determine a method for computing the amount of capacitance in a power electronic converter required to melt a fuse in the event of a line to ground fault. DC micro-grids rely on power electronic converters to change voltage levels. All converters rely on semiconductor switches that must be protected from surges of fault current. This limits the power that a converter can supply to a fuse. In many cases, sufficient power may be achieved by appropriately sizing the converters’ output capacitor.