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dc.contributor.advisorSun, Nanen
dc.creatorBautista, Harold H., 1979-en
dc.date.accessioned2012-08-13T13:55:55Zen
dc.date.available2012-08-13T13:55:55Zen
dc.date.issued2012-05en
dc.date.submittedMay 2012en
dc.identifier.urihttp://hdl.handle.net/2152/ETD-UT-2012-05-5416en
dc.descriptiontexten
dc.description.abstractBus interfaces keep getting faster and thus requiring designers to build custom physical fabrics that are able to delay clock and(or) data, on their transmitter and receivers, in order to properly receive and send data with enough setup and hold times. Delay locked loops (DLLs) have become fundamental building blocks that address such problems. Not only are they present in physical layers in integrated circuits but they also solve the problem of VLSI systems that suffer from clock skew and jitter. This report focuses on the implementation of a standard DLL and three different voltage controlled delay topologies. The different topologies are designed and compared for metrics such as linearity, delay range, and sensitivity to power supply.en
dc.format.mimetypeapplication/pdfen
dc.language.isoengen
dc.subjectDLLen
dc.subjectVCDLen
dc.subjectCurrent starveden
dc.subjectInverteren
dc.subjectManeatisen
dc.subjectPositive feedbacken
dc.titlePerformance analysis of different voltage controlled delay lines in a delay-locked loopen
dc.date.updated2012-08-13T13:56:04Zen
dc.identifier.slug2152/ETD-UT-2012-05-5416en
dc.contributor.committeeMemberGharpurey, Ranjiten
dc.description.departmentElectrical and Computer Engineeringen
dc.type.genrethesisen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorUniversity of Texas at Austinen
thesis.degree.levelMastersen
thesis.degree.nameMaster of Science in Engineeringen


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