FinFET standard cell optimization for performance and manufacturability
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As Moore's law continues to 20nm and below, traditional CMOS device faces severe short channel effects. Industry is switching from traditional CMOS to FinFET in order to keep Moore's law alive. Due to the three-dimensional structure of FinFET, many challenges need to be solved. After that, FinFET will finally be able to replace traditional CMOS in the semiconductor industry. This thesis discusses the manufacturing challenges of FinFET. In addressing these challenges, characterization of the FinFET standard cells has been done. The characterization is based on saturation current, leakage current, implantation angle and the average edge placement error at metal one layer. Three design variables, including the metal pitch, the fin pitch and the fin width are optimized to achieve better design quality. Standard cell library which contains combinatorial cells as well as sequential cells are characterized and optimized. Two optimization scenarios are included in the final results. One is performance driven, optimizing the saturation current and the leakage current, while the other is manufacturability driven, optimizing the implantation angle and the average EPE. The optimization results show the tradeoff between performance and manufacturability.