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dc.contributor.advisorSwartzlander, Earl E.en
dc.creatorSohn, Jongwooken
dc.date.accessioned2012-02-27T15:26:47Zen
dc.date.available2012-02-27T15:26:47Zen
dc.date.issued2011-12en
dc.date.submittedDecember 2011en
dc.identifier.urihttp://hdl.handle.net/2152/ETD-UT-2011-12-4722en
dc.descriptiontexten
dc.description.abstractThis report presents improved architecture designs and implementations for a fused floating-point add-subtract unit. The fused floating-point add-subtract unit is useful for DSP applications such as FFT and DCT butterfly operations. To improve the performance of the fused floating-point add-subtract unit, the dual path algorithm and pipelining technique are applied. The proposed designs are implemented for both single and double precision and synthesized with a 45nm standard-cell library. The fused floating-point add-subtract unit saves 40% of the area and power consumption and the dual path fused floating-point add-subtract unit reduces the latency by 30% compared to the traditional discrete floating-point add-subtract unit. By combining fused operation and the dual path design, the proposed floating-point add-subtract unit achieves low area, low power consumption and high speed. Based on the data flow analysis, the proposed fused floating-point add-subtract unit is split into two pipeline stages. Since the latencies of two pipeline stages are fairly well balanced the throughput of the entire logic is increased by 80% compared to the non-pipelined implementation.en
dc.format.mimetypeapplication/pdfen
dc.language.isoengen
dc.subjectDigital signal processingen
dc.subjectFloating-point arithmeticen
dc.subjectFused floating-point operationen
dc.subjectHigh speed computer arithmeticen
dc.titleImproved architectures for a fused floating-point add-subtract uniten
dc.date.updated2012-02-27T15:26:58Zen
dc.identifier.slug2152/ETD-UT-2011-12-4722en
dc.contributor.committeeMemberJohn, Lizy K.en
dc.description.departmentElectrical and Computer Engineeringen
dc.type.genrethesisen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorUniversity of Texas at Austinen
thesis.degree.levelMastersen
thesis.degree.nameMaster of Science in Engineeringen


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