Power reduction of wireless sensors networks Power reduction of wireless sensors networks
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This Master’s report presents the research leading to the development of a low power Wireless Sensor Network (WSN) and a discussion of an implementation of the WSN. This report assesses the power reduction techniques further by reviewing their influences upon functionality, throughput, latency, and data reliability. The software techniques were implemented on evaluation boards and actual performance gains were observed. Furthermore, the report provides insight into the selection of the processor, wireless protocol, and WSN architecture by comparing other options in regards to the power reduction, functionality, and data reliability. The architecture of the WSN consists of four sensor nodes, and a backbone router connected to a PC. The sensor nodes contain an application processor and a radio processor. The application processor is a Texas Instruments MSP430F5438 which is located on an MSP-EXP430F5438 evaluation board. The radio processor is a NIVIS Versa Node 210 that is located on a VS210 development board. The wireless protocol investigated is the ISA100.11a.