Thermo-mechanical stress analysis and interfacial reliabiity for through-silicon vias in three-dimensional interconnect structures
MetadataShow full item record
Continual scaling of devices and on-chip wiring has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future interconnect requirements. Among others, thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. In this dissertation, thermal stresses and interfacial reliability of TSV structures are analyzed by combining analytical and numerical models with experimental measurements. First, three-dimensional near-surface stress distribution is analyzed for a simplified TSV structure consisting of a single via embedded in a silicon (Si) wafer. A semi-analytic solution is developed and compared with finite element analysis (FEA). For further study, the effects of anisotropic elasticity in Si and metal plasticity in the via on the stress distribution and deformation are investigated. Next, by micro-Raman spectroscopy and bending beam technique, experimental measurements of the thermal stresses in TSV structures are conducted. The micro-Raman measurements characterize the local distribution of the near-surface stresses in Si around TSVs. On the other hand, the bending beam technique measures the average stress and viii deformation in the TSV structures. To understand the elastic and plastic behavior of TSVs, the microstructural evolution of the Cu vias is analyzed using focused ion beam (FIB) and electron backscattering diffraction (EBSD) techniques. To study the impacts of the thermal stresses on interfacial reliability of TSV structures, an analytical solution is developed for the steady-state energy release rate as the upper bound of the driving force for interfacial delamination. The effect of crack length and wafer thickness on the energy release rate is studied by FEA. Furthermore, to model interfacial crack nucleation, an analytical approach is developed by combining a shear lag model with a cohesive interface model. Finally, the effects of structural designs and the variation of the constituent materials on TSV reliability are investigated. The steady state solutions for the energy release rate are developed for various TSV designs and via materials (Al, Cu, Ni, and W) to evaluate the interfacial reliability. The parameters for TSV design optimization are discussed from the perspectives of interfacial reliability.