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dc.contributor.advisorAbraham, Jacob A.en
dc.creatorDutt, Samiren
dc.date.accessioned2011-07-11T20:49:07Zen
dc.date.available2011-07-11T20:49:07Zen
dc.date.issued2011-05en
dc.date.submittedMay 2011en
dc.identifier.urihttp://hdl.handle.net/2152/ETD-UT-2011-05-3585en
dc.descriptiontexten
dc.description.abstractThis thesis describes the architecture and implementation of a novel 10-bit hybrid Analog to Digital Converter using Flash and Delay Line concepts. Flash ADCs employ power hungry comparators which increase the overall power consumption of a high resolution ADC. High resolution flash also requires precision analog circuit design. Delay line ADCs are based on digital circuits and operate at low power. Both Flash based ADCs and delay line based ADCs can be used to get a fast analog to digital conversion, but with limited resolution. These two approaches are combined to achieve a 10-bit resolution (4 bits using Flash and 6 bits using delay line) without compromising on speed and maintaining low power operation. Low resolution of Flash also helps in reducing the analog circuit design complexity of the voltage comparators. The ADC was capable of running at 100M samples/s, with an ENOB of 8.82 bits, consuming 8.59mW at 1.8V.en
dc.format.mimetypeapplication/pdfen
dc.language.isoengen
dc.subjectHybrid 10-bit analog to digital converteren
dc.subjectFlash ADCen
dc.subjectVernier delay line ADCen
dc.subjectLow power ADCen
dc.subjectIntegrated circuits and systemsen
dc.titleA novel 10-bit hybrid ADC using flash and delay line architecturesen
dc.date.updated2011-07-11T20:49:13Zen
dc.identifier.slug2152/ETD-UT-2011-05-3585en
dc.contributor.committeeMemberMcDermott, Marken
dc.description.departmentElectrical and Computer Engineeringen
dc.type.genrethesisen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorUniversity of Texas at Austinen
thesis.degree.levelMastersen
thesis.degree.nameMaster of Science in Engineeringen


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