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dc.creatorRadhamohan, Ranjan Subbaraya
dc.date.accessioned2011-02-21T19:57:09Z
dc.date.accessioned2011-02-21T19:57:22Z
dc.date.available2011-02-21T19:57:09Z
dc.date.available2011-02-21T19:57:22Z
dc.date.created2010-12
dc.date.issued2011-02-21
dc.date.submittedDecember 2010
dc.identifier.urihttp://hdl.handle.net/2152/ETD-UT-2010-12-2423
dc.descriptiontext
dc.description.abstractThe application of popular image processing and classification algorithms, including agglomerative clustering and neural networks, is explored for the purpose of grouping semiconductor wafer defect map patterns. Challenges such as overlapping pattern separation, wafer rotation, and false data removal are examined and solutions proposed. After grouping, wafer processing history is used to automatically determine the most likely source of the issue. Results are provided that indicate these methods hold promise for wafer analysis applications.
dc.format.mimetypeapplication/pdf
dc.language.isoeng
dc.subjectSemiconductor
dc.subjectWafer
dc.subjectNeural
dc.subjectNetwork
dc.subjectAgglomerative
dc.subjectClustering
dc.subjectMap
dc.subjectDefect
dc.subjectYield
dc.titleAutomatic semiconductor wafer map defect signature detection using a neural network classifier
dc.date.updated2011-02-21T19:57:22Z
dc.description.departmentElectrical and Computer Engineering
dc.type.genrethesis*
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorUniversity of Texas at Austin
thesis.degree.levelMasters
thesis.degree.nameMaster of Science in Engineering


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