Compensating process and temperature variation in 32nm CMOS circuits with adaptive body bias
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As we scale down each process generation the degree of control we have on device parameters decreases. We are left to contend with a great deal of variability in process and environmental parameters. Process variation impacts dopant concentration, channel length, oxide thickness and other device parameters. Temperature variation too affects several parameters, amongst them are the threshold voltage and carrier mobility. All of these variations can either be margined for during design or compensated for dynamically. In this paper the technique of adaptive body bias is successfully applied to compensate for the variation in design so that the circuit operates at no more than 10 percent of the optimal pvt (process voltage temperature) point while minimizing leakage.