VLSI design and implementation of non-linear decoder combined with linear decompressor to achieve greater test vector compression

This paper investigates the cost-tradeoffs of implementing a test data compression technique previously presented in [Lee 06] which uses a small non-linear decoder combined with a linear decompressor to achieve greater test data compressions. The non-linear decoder is a sequential non-linear decompressor that exploits bit-wise and pattern-wise correlations in test vectors. This paper further emphasizes the design and implementation side of the proposed test data compressor. The linear decompressor used in this design is a Linear Feedback Shift Register (LFSR) which after choosing the right seed has the ability to produce the correct care bit values while filling the don’t care value bits with pseudo-random values. Experimental results show that using the presented compression scheme here significantly improves the overall compression. Area and power results are presented for the experiments carried out on the given design.