System-on-chip (SoC) design challenges - managing non-technical issues
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Efforts to increase productivity, reduce time to market, reduce costs and desire for increased functionality on a chip are driving semiconductor companies to consider SoC (System-on-a-chip) design. SoC offers the additional benefit of improving performance and design freedom. SoC designs are smaller, energy efficient and cheaper than the multi-chip solutions. Silicon manufacturing technology has improved to an extent where one can create a reliable chip with millions of transistors. Design of these complex systems, on the other hand, is taking longer and is much costlier even when the technology allows integration of the million transistor chips. Keeping these design costs low and reducing development cycle time is vital for any chip design company. Hence, companies need to delicately balance the design costs versus benefits for SoC design. Design turn-around time (TAT) even for large complex designs has been significantly improved by EDA tools despite the complexity added by the ever shrinking device geometries. However, other non technical issues and external dependencies in SoC design such as working with multi-disciplinary design teams, external IP (Intellectual Property) vendors, Electronic Design Automation (EDA) tool vendors and IP protection issues increase the risk of missing project goals and timeline. This paper will address both the technical and non-technical issues that arise when moving to SoC design and provide recommendations on how to address some of the non-technical issues involved.