Layout optimization with dummy features for chemical-mechanical polishing manufacturability
Chemical-mechanical polishing (CMP) is an enabling technique used in deep- submicron VLSI manufacturing to achieve long range planarization. Control of postCMP topography variation is crucial to meeting present and future manufacturing process challenges, like the ever decreasing depth-of-focus in photo-lithography because of aggressive scaling down of feature sizes and the ever increasing levels of interconnect due to routing complexity of more and more devices on a chip. PostCMP topography is highly dependent on design pattern in the layout. To change layout pattern to reduce within-die post-CMP topography variation, layouts need to be optimized with dummy features, which are electrically inactive. A computer-aided design (CAD) framework is first proposed to give an uni- fied view of the layout optimization process for different process models and manufacturing integration procedures. An example using the CAD framework to solve a real-world problem with hybrid tiling is given. Layout optimization with dummy features for specific areas of VLSI manufacturing using CMP is then discussed in detail. Based on recent semi-physical models of post-CMP topography and polish pad bending, the dummy feature placement problem for oxide CMP is solved with linear programming for both single-layer and multiple-layer considerations. Also, based on additional models of local pad compression and dual-material polish that are important to CMP in the shallow trench isolation (STI) process, the dummy feature placement problem is formulated as a nonlinear programming problem using a derived time-dependent relation between local pattern density and post-CMP topography. An iterative approach is then employed to solve the dummy features placement problem after simplifications of the nonlinear programming problem. Moreover, both simulated annealing and greedy approaches are used to solve the dummy feature placement problem for copper CMP in an inlaid copper interconnect process. Computational experiences with real layouts from industry for the proposed solutions to the dummy feature placement problem in oxide CMP, CMP in STI, and copper CMP all give excellent reduction in simulated post-CMP topography with reasonable run time. Experimental results on layout optimizations for oxide CMP and hybrid tiling for STI are also presented as verifications to those solutions.