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dc.creatorSanjay K. Banerjee
dc.creatorDavid L. Kencke
dc.date.accessioned2019-10-23T21:40:48Z
dc.date.available2019-10-23T21:40:48Z
dc.date.issued2001-11-06
dc.identifier.urihttps://hdl.handle.net/2152/77261
dc.identifier.urihttp://dx.doi.org/10.26153/tsw/4350
dc.description.abstractA field effect transistor such as a flash EEPROM device has channel region between a source region and a drain region with the channel region including a silicon germanium alloy layer epitaxially grown on a silicon substrate and a silicon cap layer epitaxially grown on the alloy layer. A floating gate is provided over and insulated from the channel region, and a control gate is provided over and insulated from the floating gate. The silicon germanium alloy layer and cap silicon layer provide for enhanced secondary impact ionization when injecting electrons from the channel region into the floating gate in programming the device. In a preferred embodiment the SiGe alloy layer is graded with the germanium mole fraction increasing from zero to some maximum value in the growth direction and with the germanium layer thickness being below a critical thickness for maintaining pseudomorphic strain.
dc.publisherUnited States Patent and Trademark Office
dc.relation.ispartofUniversity of Texas Patents
dc.relation.ispartofUniversity of Texas Patents
dc.titleFloating gate transistor having buried strained silicon germanium channel layer
dc.typePatent
dc.description.departmentBoard of Regents, University of Texas System
dc.rights.restrictionOpen
dc.rights.restrictionOpen
dc.contributor.assigneeBoard of Regents, The University of Texas System
dc.date.filed2000-06-15
dc.subject.cpcH01L29/7885
dc.identifier.patentnumber6313486
dc.identifier.applicationnumber9595366
dc.subject.uspc257/192
dc.subject.uspc257/191
dc.subject.uspc257/316
dc.subject.uspc257/616
dc.subject.uspc257/E29.306


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