Automated timing closure using domino logic
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One of the challenges of high speed digital circuit design has been to achieve timing closure. With shrinking geometries, more efforts have been directed towards minimizing the interconnect delay to achieve timing. However, this work presents an idea of working at the gate level to reduce the delays. Even though domino logic has been known to provide speed up to the designs, the absence of CAD tools for domino circuit design has restricted the use of domino logic as a timing closure technique just before the tape-out. This work presents a methodolgy to overcome the challenges faced in a standard "domino" cell based design flow, presenting it as an alternative/addendum to the timing closure techniques.