PLL-based digitally-intensive wireless transmitter architectures employing RF Pulse-Width Modulation
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3G and 4G wireless networks have been recently proposed for Machine to Machine (M2M) communications in order to achieve ubiquitous coverage, robust security and high reliability. The most critical design consideration in transceivers for several portable Internet of Things (IoT) wireless communication applications is often power efficiency. This poses a key design challenge in wireless transmitters for communication standards that utilize high peak-to average power ratio (PAPR) signals. In this work, two PLL-based digitally-intensive wireless transmitter architectures employing RF-Pulse Width Modulation (RF-PWM) are presented, in order to address the efficiency challenge. The first architecture employs envelope and phase information, while the second utilizes quadrature I-Q signal components directly. A key contribution of this work is the use of analog-domain Pulse-Width Modulation (PWM) that can directly generate the output signals at the desired RF band without the need for frequency up-conversion and without degradation caused by quantization. By employing Class-D output stages, the proposed architectures can provide enhanced efficiency and allow for the use of broadband loads. These approaches make the designs suitable for multi-band and multi-mode operation. Furthermore, the digitally-intensive architectures can benefit from technology scaling. A prototype RF-PWM transmitter with a Class-D power amplifier (PA) which utilizes a polar approach is implemented in a 65-nm CMOS technology. For an LTE signal with a 1.4 MHz bandwidth and a 6.4 dB peak-to-average- power ratio (PAPR), the RF-PWM transmitter achieves a power-added efficiency (PAE) of 17.5% and an adjacent channel leakage ratio (ACLR) of -30.9 dBc and -31.1 dBc at an average output power of 16.1 dBm. The proposed transmitter achieves a peak output power of 22.4 dBm with 46.6% PAE and 38.8% efficiency for the full RF-PWM transmitter, including PAs.