Analysis of electromigration in single- and dual-inlaid Cu interconnects
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The continual downward scaling of devices and increases in drive current have required an ever shrinking interconnect pitch and higher current densities. In order to overcome both the higher signal delay, as well as reliability concerns, new metallization technologies like Cu interconnects and low-k interlevel dielectrics have been developed. The implementation of inlaid Cu interconnects introduces a new set of material systems and structures which will result in new mass transport and failure mechanisms under electromigration. This study focuses on the characterization and understanding of electromigration induced failures in these advanced, 0.18 µm, Cu interconnects. Structures designed to test both the upper and lower interfaces associated with a Cu via will be used to understand the role of void formation and interconnect geometry in EM behavior. The effect of interconnect geometry is also examined using varying line width and length structures. New statistically based methodologies, using multi-link test structures, will be developed and used to further understand the reliability of these advanced interconnects. These new statistical methodologies will be applied to EM tests on both single and dual-inlaid test structures.