Statistical characterization for timing sign-off : from silicon to design and back to silicon
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With aggressive technology scaling, within-die random variations are becoming the most dominant source of process variations. Gate-level statistical static timing is becoming a widely accepted approach as an alternative to static timing analysis. However, statistical timing approaches lack good models for handling timing variations due to within-die random variations. Before performing statistical timing analysis on a design or System On Chip (SoC), the cells in the library are pre-characterized for delay as well as constraints due to these random variations. This is referred to as statistical characterization of the cells. The major contribution of this dissertation is the development of novel techniques for statistical characterization and optimization of cells. The methods couple the knowledge of circuits along with the significant factor analysis methods to compute the sensitivities, to perform statistical timing and to perform sensitivity-aware cell optimizations. The first contribution of this dissertation is a statistical delay characterization method developed for computing delay sensitivities of standard cells considering both global and mismatch process variations. In addition to the cells being characterized for delay, the sequential cells are characterized for timing constraints like setup and hold time constraints. The second contribution of this dissertation addresses the problem of constraint sensitivity characterization in sequential cells. Block-based statistical timing approaches lack accurate consideration of the impact of slew variations on both delay and arrival time variations. Specifically, the delay variations due to within-die random variables (mismatch variables) result in a slew-based correlation during timing propagation. Handling within-die random variations more accurately during statistical timing propagation is the topic of the third contribution of this dissertation. Clock networks are more prone to these within-die random variations and can result in significant clock-skew variations. In the fourth contribution, a timing margining methodology is presented that accurately accounts for the clock skew variations in a timing sign-off flow. Typically, the standard cells are designed very early in the design cycle and long before the process reaches production maturity. Any subtle improvements to reduce variability in standard cells can improve parametric yield significantly. Statistical characterization of cells for timing provides a key baseline for understanding the circuit behavior due to different sources of variation. The sensitivity information can also help increase yield by reducing the variability during the circuit design itself. The final contribution in the dissertation addresses this by defining key cell and device criticality metrics. A sensitivity-aware standard cell layout optimization is demonstrated using the proposed criticality metrics.