Bridging design and manufacturing gap through machine learning and machine-generated layout
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Very-large-scale integrated (VLSI) circuits have entered the era of 1x nm technology node and beyond. Emerging manufacturing processes such as multiple patterning lithography, E-beam lithography (EBL), and selective etching, have been proposed to ensure nano-scale manufacturability. Meanwhile, design configurations keep updating in the pursuit of performance, design flexibility, and cost reduction. Despite such advancement in design and manufacturing, the closure of design flow becomes more and more challenging. The major issues come from three aspects: (1) expensive process modeling (e.g., complex lithography systems); (2) design-dependent manufacturability (e.g., yield sensitive to design patterns); (3) complicated design constraints (e.g., numerous placement and routing rules). To close the gap between design and manufacturing, automated layout generation requires cross-layer information feed-forward and feed-back, such as accurate process modeling and manufacturing-guided design optimization. This dissertation attempts to bridge the design and manufacturing gap through synergistic design optimization for automated layout generation and efficient machine learning techniques for lithography modeling. Our research includes manufacturing aware detailed placement, holistic post-layout optimization, and learning-based lithography modeling to achieve fast design and manufacturing closure. For manufacturing aware detailed placement, the limitation of conventional flow under the context of emerging lithography technologies and design configurations, e.g., MPL, EBL, and multiple-row height standard cells, is demonstrated. Then three important directions are explored with effective algorithms and new design flows: (1) triple patterning lithography (TPL) compliance for detailed placement considering both cross-row and intra-row decomposition conflicts; (2) simultaneous EBL stitch optimization with detailed placement; (3) multiple-row detailed placement for mixed-cell-height design. For post-layout optimization, given input placement and routing solutions, layouts need to be optimized for MPL, chemical mechanical polishing (CMP), and process variations, without affecting the functionality and performance of the designs. In particular, the following critical challenges are identified and resolved: (1) efficient and high-quality layout decomposition; (2) holistic dummy fill insertion to balance layout uniformity and coupling capacitance; (3) patterning aware design optimization for selective etching. The study focuses on yield improvement with manufacturing-guided layout manipulation and developing effective yet efficient approaches for even NP-hard problems such as layout decomposition. For lithography modeling, one of the major conflicts in modeling is considered: accuracy and amounts of calibration data. Models often rely on huge amounts of calibration data to achieve generality and high accuracy on a large variety of design patterns, while obtaining manufacturing data is usually expensive and time-consuming. With the observation of the potential correlation between datasets from consecutive technology nodes, a transfer learning scheme is proposed, leveraging existing data from an old technology node to help the calibration of the target technology node. Then an effective active learning algorithm with theoretical insights is also developed to actively select representative data for model calibration. With our machine learning techniques, a significant reduction on data is possible while maintaining high modeling accuracy. The effectiveness of proposed design optimization and machine learning techniques is demonstrated with extensive experiments on industrial-strength benchmarks. Our approaches are capable of reducing turn-around time, saving modeling costs, and enabling fast design and manufacturing closure.