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dc.contributor.advisorGharpurey, Ranjit
dc.creatorHung, Cheng-Hsien
dc.date.accessioned2018-03-21T14:29:14Z
dc.date.available2018-03-21T14:29:14Z
dc.date.created2015-12
dc.date.issued2015-12-04
dc.date.submittedDecember 2015
dc.identifierdoi:10.15781/T29W09G19
dc.identifier.urihttp://hdl.handle.net/2152/63897
dc.description.abstractDemands for high data-rate communications and high-precision sensing applications have pushed wireless systems towards higher operating frequencies where wider bandwidth is available. Examples of such applications include 60 GHz indoor communications and vehicular RADAR around 77 GHz. High-speed frequency synthesizers integrated in a CMOS process, with wide operating bandwidth, and low phase noise are key to low-cost transceiver implementations for such applications. The requirement to operate over a wide span of carrier frequencies arises from two key sources. The system itself often requires a wide tuning range, in excess of 5-10% of the carrier frequency. Further, it is necessary to compensate for the uncertainty in operating frequencies, caused by process and temperature variations. This dissertation introduces a dual-mode voltage-controlled oscillator (VCO) topology, embedded in a frequency synthesizer, for wideband operation. The VCO can operate in two oscillation modes by reconfiguring the active negative resistance core around the LC tank that is employed as the resonator element in the oscillator. A key aspect to the design is that the switches used for mode reconfiguration do not contribute to the tank loss. The frequency spacing of the two modes is determined by an accurate inductor ratio. It is demonstrated through analysis that in order to ensure mode-switching, the size of the switches needs be larger than a critical value, which is a function of the electrical properties of the cross-coupled, negative resistance core, as well as the resonator used in the design. The impact of noise injection and mismatch on switching behavior is also analyzed. The VCO topology has been implemented in a 65nm CMOS process. The design demonstrates measured tuning ranges of 56.9 GHz to 65.4 GHz, and 64.6 GHz to 75.3 GHz, in the two respective modes, for a total effective tuning range of 28%. The oscillator consumes 13 mW, with a 1 V-supply, and its Figure of Merit with tuning range (FOMT) is -177.2 dB. An integer-N frequency synthesizer that employs the dual-mode VCO, has also been designed and verified in a 65 nm CMOS process. The synthesizer has a locking range from 56 GHz to 63.9 GHz in its low frequency mode. The total power consumption of the synthesizer, including output buffers, is approximately 50 mW. The in-band phase noise, at a locked frequency of 63.04 GHz, is -88.4 dBc/Hz at 1 MHz offset.
dc.format.mimetypeapplication/pdf
dc.language.isoen
dc.subjectDual-mode
dc.subjectVCO
dc.subjectOscillator
dc.subjectPhase noise
dc.subjectTuning range
dc.subjectVaractor
dc.subjectPLL
dc.subjectMillimeter-Wave
dc.subjectWideband
dc.subjectFrequency synthesizer
dc.titleReconfigurable dual-mode voltage-controlled oscillator and wideband frequency synthesizer for millimeter-wave applications
dc.typeThesis
dc.date.updated2018-03-21T14:29:14Z
dc.contributor.committeeMemberAlù, Andrea
dc.contributor.committeeMemberOrshansky, Michael
dc.contributor.committeeMemberSun, Nan
dc.contributor.committeeMemberRudell, Jacques Christophe
dc.description.departmentElectrical and Computer Engineering
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorThe University of Texas at Austin
thesis.degree.levelDoctoral
thesis.degree.nameDoctor of Philosophy
dc.type.materialtext


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