van der Waals epitaxy and electronic transport in topological insulators
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Topological insulators (TI) have been demonstrated as a unique electronic phase of matter, possessing topological surface states (TSS) with promising applications in spin-based logic and memory, heterostructures in 2D electronics and exotic physical phenomena such as Majorana quantum computing, axion electrodynamics and topological magnetoelectronics. Since the early stages of discovery, the field of applied research in TIs has evolved. However, demonstration of scalable applications remain challenging due to practical hurdles such as rapid prototyping of new TI compounds, and efficient probing of TSS for device applications. This research work endeavors to take a two-pronged approach: to address the challenges of reliable material growth and to explore TI transport physics. While indirect spectroscopy methods have indisputably shown the presence of TSS, transport in TI devices remains challenging, in part due to parasitic conduction channels. As an alternative to staple binaries, ternary and quaternary compounds (Bi₁₋[subscript y]Sb[subscript y])₂(Te₁₋[subscript x]Se[subscript x])₃ are being explored to reduce unintentional bulk-doping and gain better access to the Dirac point. The sulfur-based ternary Bi₂Te₂S has received little attention, even as its potential as a promising TI is theoretically predicted. We demonstrate first-time van der Waals epitaxial (vdWE) growth of crystalline Bi₂Te₂₋[subscript x]S₁₊[subscript x] (BTS) nanosheets on SiO₂, hBN and mica. We also perform detailed magnetotransport measurements on BTS devices, establishing BTS as a candidate TI with readily accessible TSS and providing a sound picture of multiple transport channels in TI devices. A versatile process for large-area custom-feature TI growth and fabrication is also demonstrated using BTS as the candidate TI, achieved through selective-area modification of surface free-energy on mica. TI features grow epitaxially in large single-crystal trigonal domains, exhibiting armchair or zigzag edges highly oriented with the substrate lattice. Unusual nonlinear thickness dependence on lateral dimensions and denuded zones are observed, explained by semi-empirical two-species surface migration modeling with robust estimates of growth parameters. TSS contribute up to 60% of device conductance at room-temperature, indicating excellent electronic quality. The process is constructed from highly adaptable microfabrication technology, and in conjunction with multi-species modeling, it can be customized for TI and other vdW materials device fabrication processes ranging from rapid prototyping to scalable manufacturing.