Controlling work in process during semiconductor assembly and test operations
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In the semiconductor industry, products go through a series of steps over a three- to four-month period that begins with the fabrication of chips and ends with assembly and test (AT) and shipment. This paper introduces a mid-term planning model for scheduling AT operations aimed at minimizing the difference between customer demand and product completions each day. A secondary objective is to maximize daily throughput. Typically, semiconductor companies have 1000s of products or devices in their catalog that can be organized into unique groups of up to 100 devices each. This simplifies the planning process because it is only necessary to consider the groups as a whole rather than the individual devices when constructing schedules. In all, we developed and tested three related models. Each provides daily run rates at each processing step or logpoint for each device group for up to one month at a time. The models are distinguished by how cycle time is treated. The first takes a steady-state approach and uses Little’s Law to formulate a WIP target constraint based on the average cycle time at each processing step. The second and third include integer and fractional cycle times in the variable definitions. To find solutions, raw production data are analyzed in a preprocessing step and then converted to input files in a standard format. FlopC++ from the COIN-OR open source software project is used to write and solve the model. Testing was done using three datasets from the Taiwan AT facility of a global semiconductor firm. By comparing model output with historical data for 6 device groups and 33 logpoints, we were able to realize decreases in shortages of up to 40% per month.