Shmoo analysis of integrated circuits using machine learning algorithms
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High Volume Manufacturing (HVM) testing of microprocessors use a variety of means to verify that a product meets the specification. One of such means is the use of Shmoo plots. Shmoo plot analysis of microprocessors is a common way of characterizing a processor over a range of parameters such as supply voltage, clock frequency and temperature. When a defect occurs, the Shmoo plots are collected on a tester over multiple process corners and manual data review occurs to identify marginality and corner cases. This problem can get magnified when debugging yield problems. There is a need to be able to review Shmoo plots in a very short time cycle to eliminate processors with process random defects or design marginality before they reach the consumers and identify any test holes. For my thesis I develop a tool that uses a machine learning based model to predict the failing points on a Shmoo plot of a microprocessor. The objective of this tool is to reduce the time of Shmoo analysis by mimicking the behavior of a tester and ultimately reduce Post-silicon test time. The tool can be added to any existing test flow process. The first part of my thesis describes the setup of the model and the different machine learning algorithms used. Then I evaluate the performance of each algorithm and make a recommendation on what algorithm to use for this particular problem. Finally, I analyze the effects of each feature on the recommended algorithm and look at the distribution of mis-predicted points across each feature. The experiments show promising accuracy and timing results for the selected algorithm. Furthermore this methodology can be integrated into any existing HVM test flow.