Skip to main content
English
Català
Čeština
Deutsch
Español
Français
Gàidhlig
Italiano
Latviešu
Magyar
Nederlands
Polski
Português
Português do Brasil
Srpski (lat)
Suomi
Svenska
Türkçe
Tiếng Việt
Қазақ
বাংলা
हिंदी
Ελληνικά
Српски
Yкраї́нська
Log In
Log in with UT EID
Log in
Have you forgotten your password?
Communities & Collections
All of TSW
Statistics
English
Català
Čeština
Deutsch
Español
Français
Gàidhlig
Italiano
Latviešu
Magyar
Nederlands
Polski
Português
Português do Brasil
Srpski (lat)
Suomi
Svenska
Türkçe
Tiếng Việt
Қазақ
বাংলা
हिंदी
Ελληνικά
Српски
Yкраї́нська
Log In
Log in with UT EID
Log in
Have you forgotten your password?
Repository Home
UT Electronic Theses and Dissertations
UT Electronic Theses and Dissertations
Voltage and temperature dependent gate capacitance and current model for high-K gate dielectric stack
Voltage and temperature dependent gate capacitance and current model for high-K gate dielectric stack
Access full-text files
fany029.pdf
(1.1 MB)
Date
2002
Authors
Fan, Yang-yu
Journal Title
Journal ISSN
Volume Title
Publisher
Abstract
Department
Electrical and Computer Engineering
Description
text
Keywords
LCSH Subject Headings
Gate array circuits
,
Dielectrics
,
Metal oxide semiconductor field-effect transistors
Citation
URI
http://hdl.handle.net/2152/567
Collections
UT Electronic Theses and Dissertations
Full item page