Concurrent error detection for two level circuits with area reduction based on over-approximation
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As process technology continues to scale down, there is an increased susceptibility to Single Event Upsets(SEUs) leading to soft errors. Various methods which implement Concurrent Error Detection(CED) have been proposed to address this problem. One of the key drawbacks with CED using full duplication is the high area overhead incurred. In this work, we propose an approach that uses overapproximation to minimize the detection circuitry thus providing significant area reduction with negligible fault coverage loss. An issue with over-approximating the detection circuitry is that false negatives can occur. We present a novel methodology to keep track of such cases and selectively ignore them. Our work involves altering the two level logic minimization tool ESPRESSO-II to efficiently guide the modification of the logic function being implemented so as to provide maximum area benefits, constrained by an allowable fault coverage loss. A set of experimental results demonstrate the area-coverage tradeoffs that can be achieved.