Pseudo pipelined SAR ADC with regenerative amplifier
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The power consumption of Analog to digital converters (ADCs) is an important design criterion in today’s market of wireless and battery operated stand alone systems. Successive approximation register (SAR) ADCs do very well in this regard and have been designed with excellent figures of merit with respect to power. However, their speeds of operation are low. Pipelined ADCs have been known to do very well where speed and performance are important criteria. There have been multiple works where combinations of the two have been used in order to leverage on the benefits of each. This work explores the different options we have in implementing the residue amplifier in a two stage pipelined ADC. A linear op-amp is traditionally used to implement the residue amplifier. Integrators have been used for this purpose as well. This design takes it one step further and explores the feasibility of using positive feedback amplification in order to achieve the function of the residue amplifier. The challenges and concepts of this new design architecture are explored. A test chip will be fabricated with this design as well and its performance in silicon will be published at a later time.